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ISL97701
Data Sheet February 22, 2008 FN6474.1
Boost Regulator with Integrated Schottky and Input Disconnect Switch
The ISL97701 represents a high efficiency boost converter with integrated boost FET, boost diode and input disconnect FET. With an input voltage of 2.3V to 5.5V the ISL97701 has an output capability of up to 50mA at 18V using integrated 500mA switches. Efficiencies are up to 87%. The integrated protection FET is used to disconnect the boost inductor from the input supply whenever an output fault condition is detected, or when the device is disabled. This gives 0 output current in the disabled mode, compared to standard boost converters where current can still flow when the device is disabled. The ISL97701 comes in the 10 Ld 3x3 DFN package and is specified for operation over the -40C to +85C temperature range.
Features
* Up to 87% efficiency * 2.3V to 5.5V input * Up to 28V output * 50mA at 18V * Integrated boost Schottky diode * Input voltage disconnect switch * Synchronization input * Chip enable * 10 Ld 3x3 DFN package * Pb-free (RoHS compliant)
Applications
* OLED display power * LED display power * Adjustable power supplies
Ordering Information
PART NUMBER (Note) ISL97701IRZ ISL97701IRZ-T7* ISL97701IRZ-T13* PART MARKING 977 01IRZ 977 01IRZ 977 01IRZ PACKAGE (Pb-free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN PKG. DWG. # MDP0047 MDP0047 MDP0047
Typical Application Diagram
L1 6.8H VDDOUT 2.3V TO 5.5V C0 5F NEN NSYNC GND FB R2 39k LX VDD OSCILLATOR AND CONTROL VOUT VDD+2V TO 30V C1 3.3F R1 390k
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL97701 (10 LD 3X3 DFN) TOP VIEW
NOTE: VOUT = (390k + 39k)/39k*1.15V = 12.65V
GND 1 VDDOUT 2 VDD 3 NSYNC 4 FB 5 THERMAL PAD
10 LX 9 VOUT 8 NEN 7 GND 6 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97701 Block Diagram
VDD
SYNCHRONIZATION SIGNAL DETECTOR 1 OSCILLATOR MUX 0 CLK START
OVER-TEMPERATURE DETECTOR
UNDERVOLTAGE DETECTOR OVERCURRENT DETECTOR (DC) S2
VDD
NSYNC
VDD NEN
GND
RESTART DISABLE AND WAIT STATE MACHINE (DEFAULT SEQUENCE) 1. SOFT INRUSH 2. VDDOUT ENABLE 3. SOFT BOOST 25 4. SOFT BOOST 50 5. SOFT BOOST 75 6. NORMAL
VDDOUT
2
OVERVOLTAGE DETECTOR
VOUT
SLOPE COMPENSATION RAMP-GENERATOR ERROR AMP + FB VOLTAGE REFERENCE ISL97701
+ As + Av + Ai -
EN
LX GATE DRIVER CURRENT LIMIT COMPARATOR
=0
CONTROL LOGIC -PWM TIMING -CURRENT LIMIT -PULSE SKIPPING
CCOMP CLAMP
RSENSE GND
FIGURE 1. ISL97701 BLOCK DIAGRAM
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FN6474.1 February 22, 2008
ISL97701
Absolute Maximum Ratings (TA = +25C)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V VOUT to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 31V LX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VOUT + 1V VDDOUT, NSYNC, FB, NEN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Continuous Current in VDD, GND, VDDOUT, LX . . . . . . . . . 650mA Continuous Current in NSYNC, FB, NEN . . . . . . . . . . . . . . . . 10mA
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 10 Ld 3x3 DFN Package . . . . . . . . . . . 48 7 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature (TA) . . . . . . . . . . . .-40C to +85C Operating Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . +125C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +130C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER SUPPLY VDD IDIS
VDD = 3.6V, GND = NEN = 0V, NSYNC = VDD, R1 = 390k, R2 = 39k, L = 10H, TA = -40C to +85C unless otherwise stated. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Supply Operating Voltage Range Supply Current when Disabled NEN = VDD
2.3 0.1
5.5 3
V A
LOGIC INPUTS - NEN, NSYNC RUP IIL VHI VLO Pull-up Resistor Leakage Current when Disabled Logic High Threshold Logic Low Threshold Enabled, Input at GND Disabled, Input at GND 150 -1 1.8 0.7 250 350 1 k A V V
POWER-ON RESET - VDD VRES_ON VRES_OFF Power-On Reset Threshold Power-Off Threshold VDD rising VDD falling 1.9 2.2 2 2.3 V V
LX OUTPUT DRIVER fOSC fSYNC tON-MIN tOFF-MIN rON ILEAK IPEAK LX Switching Frequency with Internal Oscillator LX Switching Frequency when Externally Synchronized at NSYNC Minimum On-Time Minimum Off-time ( Maximum Duty Cycle) LX ON-Resistance LX Leakage Current LX Peak Current Limit FB = 0V, I(LX) > Ilim(LX) FB = 0V, I(LX) < Ilim(LX) I(LX) = 100mA NEN = VDD, V(LX) = 30V t > 8.32ms (end of soft-start) 0.9 1 f (NSYNC) 60 60 0.4 1 1200 5 ns ns A mA 1.1 MHz
SCHOTTKY DIODE - LX, VOUT VDIODE Forward Voltage from LX to VOUT I = 10mA, TA = +25C I = 10mA, TA = -40C to +85C 0.4 0.3 0.5 0.5 0.6 0.7 V V
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FN6474.1 February 22, 2008
ISL97701
Electrical Specifications
PARAMETER FEEDBACK INPUTS VrefFB Input Reference Voltage on FB TA = +25C TA = -40C to +85C IFB RFB Input Current in FB FB Pull-Down Switch Resistance FB = 1.3V IFB = 10mA 1.13 1.12 -0.2 15 1.15 1.15 1.17 1.18 0.2 25 V V A VDD = 3.6V, GND = NEN = 0V, NSYNC = VDD, R1 = 390k, R2 = 39k, L = 10H, TA = -40C to +85C unless otherwise stated. (Continued) CONDITION MIN TYP MAX UNIT
DESCRIPTION
SYNCHRONIZATION INPUT - NSYNC fNSYNC tdNSYNC External Sync Frequency Range NSYNC Falling Edge to LX Falling Edge Delay fNSYNC = 600kHz 600 80 1400 100 kHz ns
OVERVOLTAGE DETECTOR - VOUT VOUT Overvoltage Threshold FB = GND 31 35 V
OVERCURRENT DETECTOR IOCTVDDOUT Overcurrent Threshold t > 2.048ms, DC current 800 mA
OVER-TEMPERATURE DETECTOR tOFF tON Shut-Down Temperature Threshold Turn-On Temperature Threshold T rising T falling 135 100 C C
FAULT SWITCH - VDD, VDDOUT rONFS IleakVDDOUT ISS_VDDOUT REGULATION ACC Output Voltage Accuracy, Assuming Resistor Divider Tolerances of 0.1% or Better Load Regulation Line Regulation IOUT = 10mA, TA = +25C IOUT = 10mA, TA = -40C to +85C IOUT = 0mA to 50mA VDD = 3.6V to 2.6V, IOUT = 30mA -1.5 -2.5 0.05 0.1 1.5 2.5 % % % %/V ON-Resistance from VDD to VDDOUT Leakage Current Soft Inrush Current Source at VDDOUT IOUT = 50mA, t > 2.048ms VDDOUT = 0V VDD - VDDOUT = 0.5V, tON < 2.048ms 0.2 0.01 50 3 A mA
VOUT/IOUT VOUT/VDD
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FN6474.1 February 22, 2008
ISL97701 Typical Performance Curves
90 4.2V 85 EFFICIENCY (%) EFFICIENCY (%) 85 90 4.2V
80 2.7V 75
3.6V
80 2.7V 75
3.6V
70
70
65 0 50 100 150 LOAD CURRENT (mA)
65 0 50 IOUT (mA) 100 150
FIGURE 2. EFFICIENCY vs LOAD CURRENT (VOUT = 18.3V) L = 10H (CDRH4D28C-100NC) C = 6.6F
FIGURE 3. EFFICIENCY vs IOUT (VOUT = 18.3V) L = 6.8H (TDK RLF7030) C = 6.6F
90 4.2V 85 EFFICIENCY (%) 3.6V 80 2.7V EFFICIENCY (%)
90 4.2V 85 3.6V 80 2.7V
75
75
70
70
65 0 50 100 IOUT (mA) 150 200
65 0 50 100 IOUT (mA) 150 200
FIGURE 4. EFFICIENCY vs IOUT (VOUT = 12.6V) L = 6.8H (TDK RLF7030) C = 6.6F
FIGURE 5. EFFICIENCY vs IOUT (VOUT = 12.7V) L = 10H (CDRH4D28C-100NC) C = 6.6F
V(NEN)
V(NEN)
V(VOUT)
V(VOUT)
I(VDD) I(VDD)
FIGURE 6. START-UP TO 12V (VDD = 3.6V, RL = 360)
FIGURE 7. START-UP TO 18V (VDD = 3.6V, RL = 360)
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FN6474.1 February 22, 2008
ISL97701 Typical Performance Curves
V(NEN) 18.20 18.19 18.18 18.17 V(VOUT) VOUT (V) I(VDD) 18.16 18.15 18.14 18.13 18.12 18.11 18.10 18.09 0 50 100 150
(Continued)
LOAD CURRENT (mA)
FIGURE 8. SHUTDOWN (VDD = 3.6V, RL = 360)
FIGURE 9. LOAD REGULATION (VIN = 3.6V)
18.29 18.28 18.27 VOUT (V) 18.26 18.25 18.24 18.23 2.6 QUIESCENT CURRENT (A)
1200 1000 800 600 400 200 0
3.1
3.6
4.1
4.6
5.1
0
1
2
3 VIN (V)
4
5
6
VIN (V) FIGURE 10. LINE REGULATION (IOUT = 30mA)
FIGURE 11. QUIESCENT CURRENT vs VIN
3.2 2.9 2.6 2.3 POUT (W) 2.0 1.7 1.4 1.1 0.8 0.5 2.3 (CH1 = VOUT; CH4 = iL; CH2 = IOUT) 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 5.1 5.5
FIGURE 12. TRANSIENT RESPONSE (VIN = 3.3V; VOUT = 18.3V; STEP LOAD CURRENT FROM 2.6mA TO 70mA)
FIGURE 13. RECOMMENDED MAXIMUM OUTPUT POWER vs INPUT VOLTAGE
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FN6474.1 February 22, 2008
ISL97701 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME GND VDDOUT VDD NSYNC FB NC GND NEN VOUT LX Ground Protection Switch Output Supply Input Synchronization Input (Falling Edge) Feedback Input Do Not Connect Ground Enable Input (Active Low) Boost Output Voltage Boost FET PIN FUNCTION
When NEN is driven low the ISL97701 begins with the start-up sequence.
Start-Up Sequence
After pin NEN is pulled low or a restart is triggered from Fault Control during operation, the ISL97701 goes through a startup sequence with the following six states: Soft Inrush -> VDDOUT Enable -> Soft Boost 25 -> Soft Boost 50 -> Soft Boost 75 -> Normal. If the sequence has completed, the ISL97701 stays in the "Normal" state until NEN is high again or any fault is detected. SOFT INRUSH: STATE DURATION ~2.048ms The switch at VDDOUT is configured as current source and provides a limited current through the inductor to pre-charge the capacitor at VOUT. VDDOUT ENABLE: STATE DURATION ~128s The switch at VDDOUT is fully enabled and connects the inductor to VDD with a low ON-resistance. SOFT BOOST 25 -> 50 -> 75: STATE DURATION 3x ~2.048ms The boost regulator begins to switch at LX. The LX current limit increases in three steps representing 25%, 50% and 75% of its final value. NORMAL If no fault was detected Normal state is entered ~8.256ms after NEN is pulled low. The LX current limit steps up to 100%. In all states Fault Control can force the sequence to restart or even to shutdown (see Table 1).
V(NEN)
Function Overview
The ISL97701 is a high frequency, high efficiency boost regulator which operates in constant frequency PWM mode. The boost converter generates a stable, higher output voltage from a variable, low voltage input source (e.g. Li-ion battery). The output voltage level is defined from the feedback resistor network in Equation 1.
V OUT = V refFB * ( R 1 + R 2 ) R 2 (EQ. 1)
The switching frequency is either generated from the fixed 1MHz internal oscillator or provided externally at the synchronization pin in the range from 600kHz to 1.4MHz. The compensation network and soft-start functions are built in with fixed parameters without any need for further external components. To stop battery discharge into the output load when disabled, the inductor is disconnected from the input supply with a low ON-resistance power switch. Built-in fault protection monitors inductor current and output voltage as well as junction temperature in order to interrupt the high current circuit path through the inductor and diode in the event of a load failure. Low logic input thresholds allow the ISL97701 to interface directly to microcontrollers with lower supply voltage. Alternatively, the internal pull-up resistors on all logic inputs provide level shifting when driven from open collector outputs.
V(VOUT)
NORMAL 75 50 25 VDDOUT ENABLE
I(VDD)
Description of Operation
Enable Pin (Active Low) - NEN
If NEN is high, the ISL97701 shuts down all its internal functions and deactivates its I/So. Only the internal pull-up resistor at NEN remains active. If NEN is high, the input disconnect switch between VDD and VDDOUT interrupts the circuit path from the input voltage VDD through inductor and diode to the output load at VOUT. If shutdown, the total supply current in VDD is typically less than 0.1A.
SOFT INRUSH
FIGURE 14. FAULT CONTROL SEQUENCE
Fault Control
The input voltage at VDD, current in the VDDOUT switch, voltage at VOUT and junction temperature TJ are continuously monitored and can either restart the start-up
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FN6474.1 February 22, 2008
ISL97701
sequence or in some cases disable the ISL97701 boost function as long as the fault is present.
TABLE 1. FAULT PROTECTION FAULT DESCRIPTION Undervoltage at VDD Overcurrent drawn from VDDOUT Overvoltage at VOUT FAULT CONDITION V(VDD) < V(VDD)off ISL97701 FAULT REACTION Disables I/Os and waits until V(VDD) reaches V(VDD)on to begin with the start-up sequence
pin is, for example, static high, the internal oscillator defines the LX output frequency and phase. When externally synchronized, all falling edges at LX are timed from the falling edge of the clock signal applied at NSYNC. The timing of the rising edge at LX is defined by the boost controller.
V(NSYNC)
I(VDDOUT) > Disables VDDOUT switch and It(VDDOUT)err LX driver and immediately restarts the start-up sequence V(VOUT) > Vt(VOUT)err Disables VDDOUT switch and LX driver and waits until output voltage V(VOUT) drops to Vt(VOUT) to restart the start-up sequence Disables VDDOUT switch and LX driver and waits until junction temp drops to "Ton" to restart the start-up sequence FIGURE 15. NSYNC TO LX SYNCHRONIZATION DELAY
V(LX)
Over-Temperature Tj > Toff on chip
Maximum Duty Cycle - LX
The maximum duty cycle Dmax, at which the power FET can operate defines the upper limit of the regulator output to input voltage ratio according to Equation 2:
V OUT 1 --------------- = ------------------------1 - DMAX V IN (EQ. 2)
V(NSYNC)
In the ISL97701, DMAX is defined from the minimum off-time tOFF(LX)min and the switching frequency. If NSYNC is tied to VDD the internal oscillator defines DMAX according to Equation 3:
D MAX ( f OSC ) = 1 - t OFF ( LX )min * f OSC (EQ. 3)
V(LX)
With external synchronization at pin NSYNC:
D MAX ( NSYNC ) = 1 - t OFF ( LX )min * f ( NSYNC ) (EQ. 4) FIGURE 16. LX SYNCHRONIZATION WITH f(SYNC) = 600kHz
The duty cycle at LX can be 0% (pulse skipping), if the output voltage exceeds the target voltage set with the feedback resistors.
V(NSYNC)
Internal Schottky Diode - LX, VOUT
The inductor node LX internally connects to the power FET and to the anode of the integrated power Schottky diode. The cathode of the diode is pin VOUT. An overvoltage detector at VOUT continuously monitors the cathode voltage and immediately disables the boost regulator if the voltage exceeds the maximum allowable voltage.
V(LX)
External Synchronization Pin - NSYNC
Pin NSYNC can be used to synchronize the LX output pin with an external clock signal in the range from 600kHz to 1.4MHz. A frequency detector monitoring NSYNC enables external synchronization if f(NSYNC) is higher than ~300kHz. If the 8
FIGURE 17. LX SYNCHRONIZATION WITH f(SYNC) = 1.4MHz
FN6474.1 February 22, 2008
ISL97701
C7 3.3F/50V R1 390k J7
C8 100nF
VOUT C6 1nF/50V
J2 U1 1 J1 VDD_IN C1 VDD 100nF JP3 VDD C2 10F 2 3 4 C9 4.7F/10V 5
L1 6.8H J3 R6 39k R3 OPEN VDD 1 J6 J1 2 3 NEN
GND_IN
LX 10 VDDOUT 9 VOUT VDD 8 NEN NSYNC 7 GND FB 6 NC GND ISL97701
GND_OUT
J4 NSYNC
FIGURE 18. ISL97701 APPLICATION BOARD
Typical Application
Typical applications are passive- or active-matrix organic light emitting diode displays (PMOLED, AMOLED) in handheld devices. Applications with low power or screen saver mode is directly supported.
TABLE 2. OPTIMAL COMBINATION OF BOOST INDUCTOR L AND OUTPUT CAPACITOR COUT CAPACITOR (F) INDUCTOR (H) 4.7 MIN 2.2 3.3 4.7 6.8 MAX 10 10 10 10
Components Selection
The input capacitance is normally 10f~15F and the output capacitor is 3.3f to 6.6F. X5R or X7R type of ceramic capacitor with correct voltage rating is recommended. The output capacitor value will affect the output voltage ripple. The higher the value of the output capacitor, the lower the ripple of the output voltage. When choosing an inductor, make sure the inductor can handle the average and peak currents given by Equations 5, 6 and 7 (80% efficiency assumed):
I OUT V OUT I LAVG = --------------------------------0.8 V IN (EQ. 5) TDK: Toko: 1 I LPK = I LAVG + -- I L 2 V IN ( V OUT - V IN ) I L = -------------------------------------------------L V OUT f OSC (EQ. 6)
6.8 10 15
Recommended inductor and ceramic capacitor manufacturers are listed in Table 3:
TABLE 3. RECOMMENDED INDUCTOR AND CERAMIC CAPACITOR MANUFACTURERS INDUCTOR Sumida: www.sumida.com www.tdk.co.jp www.tokoam.com CERAMIC CAPACITOR Taiyo Yuden: www.t-yuden.com AVX: Murata: www.avxcorp.com www.murata.com
PCB Layout Considerations
The layout is very important for the converter to function properly. To ensure the high pulse current in the power ground does not interfere with the sensitive feedback signals, the current loops (VIN-L1-LX-GND, and VIN-L1VOUT-COUT-GND) should be as short as possible. For the DFN package, there is no separated GND. All return GNDs should be connected in GND pin but with no sharing branch. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for the EMI performance.
(EQ. 7)
Where: * IL is the peak-to-peak inductor current ripple in Amperes * L is the inductance in H * fOSC is the switching frequency, typically 1.0MHz Optimal combinations of the boost inductor L and the output capacitor COUT are listed in Table 2:
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FN6474.1 February 22, 2008
ISL97701 Dual Flat No-Lead Package Family (DFN)
A D N N-1 0.075 C 2X E PIN #1 I.D.
MDP0047
DUAL FLAT NO-LEAD PACKAGE FAMILY (JEDEC REG: MO-229) MILLIMETERS SYMBOL A A1 b c
1 2 0.075 C
DFN8 0.85 0.02 0.30 0.20 4.00 3.00 4.00 2.20 0.80 0.50 0.10
DFN10 0.90 0.02 0.25 0.20 3.00 2.25 3.00 1.50 0.50 0.50 0
TOLERANCE 0.10 +0.03/-0.02 0.05 Reference Basic Reference Basic Reference Basic 0.10 Maximum Rev. 2 2/07
D D2 E
B TOP VIEW
2X
4 L1
(D2)
E2 e
N-1
N L (N LEADS)
L L1 NOTES:
(E2)
1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Exposed lead at side of package is a non-functional feature.
PIN #1 I.D. 2 5 e b BOTTOM VIEW 1 0.10 M C A B 3
3. Bottom-side pin #1 I.D. may be a diepad chamfer, an extended tiebar tab, or a small square as shown. 4. Exposed leads may extend to the edge of the package or be pulled back. See dimension "L1". 5. Inward end of lead may be square or circular in shape with radius (b/2) as shown. 6. N is the total number of leads on the device.
0.10 C SEATING PLANE 0.08 C
C
SEE DETAIL "X"
(N LEADS & EXPOSED PAD)
2 C A (c)
A1 DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6474.1 February 22, 2008

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